Space Systems Engineering Integration & Test Engineer - TIDES FPGA (PIE)

Basic Qualifications

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience.

CLEARANCE REQUIREMENTS:

Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

ROLE AND POSITION OBJECTIVES:

As a Systems Engineering Integration & Test Engineer - TIDES FPGA, you will be a member of the Payload Integration and Evolution (PIE) team within SEIT’s organization. The PIE team develops and evolves the Payload Verification Platform (PVP), a hardware development environment made up of COTS and custom FPGA boards, development kits, and supporting infrastructure used to emulate spacecraft payload behavior for early integration, risk reduction, and test software development.

In this role, you will help define, architect, and lead FPGA-enabled capabilities for the PVP, from early requirements and microarchitecture through RTL implementation, simulation, timing closure, interface integration, and lab bring-up. Your work will mature reusable test infrastructure that bridges test equipment with units under test, enables real-time functions such as packet timestamping and precision command scheduling, and supports payload programs as they move from early development toward verification and flight readiness.

Key Responsibilities

Lead FPGA-supported development and integration activities for the Payload Verification Platform (PVP) as part of the Payload Integration and Evolution (PIE) team within SEIT’s TIDES organization

Architect, design, integrate, and mature COTS and custom FPGA-based development platforms used to emulate spacecraft payload behavior for early integration, risk reduction, and test software development

Define FPGA and hardware integration approaches that bridge test equipment, payload hardware, and software infrastructure

Lead RTL development, simulation, interface integration, timing closure support, and lab bring-up for FPGA-enabled test capabilities

Drive real-time test functions such as payload interface emulation, packet timestamping, precision command scheduling, and protocol translation

Collaborate with systems, electrical, software, test, and program teams to derive platform requirements and resolve integration issues

Lead structured debug efforts using lab instrumentation, waveform analysis, software tools, and root-cause investigation

Mentor junior engineers and contribute to design reviews, integration planning, technical roadmaps, and platform evolution

Document architecture, interface definitions, bring-up procedures, release artifacts, and lessons learned

Preferred Skills & Experience

Bachelor’s degree in Electrical Engineering, Computer Engineering, Systems Engineering, or a related technical field

Significant experience with FPGA design, RTL development, hardware integration, and lab bring-up

Proficiency with SystemVerilog and/or VHDL, simulation, timing constraints, and FPGA vendor toolchains such as Vivado, Lattice Diamond/Radiant, or equivalent

Experience integrating FPGA interfaces such as Ethernet, SPI, UART, JESD204B/C, high-speed serial links, or custom board-level protocols

Strong understanding of digital design, clock-domain crossing, reset strategy, synchronous/asynchronous interfaces, and timing closure

Hands-on experience with lab equipment such as oscilloscopes, logic analyzers, JTAG, protocol analyzers, and waveform capture tools

Experience working across systems, hardware, software, and test teams to define requirements and drive integration closure

Proficiency with scripting and automation using Python, Tcl, Linux shell, or similar tools

Experience with Linux environments, Git-based workflows, CI/CD pipelines, and controlled FPGA artifact release processes

Familiarity with payload integration, hardware development environments, spacecraft electronics, or verification platforms is strongly preferred

What Sets You Apart

You think at the platform level and understand how FPGA design decisions affect payload integration, test software, lab operations, and program execution

You can move comfortably between architecture, RTL, simulation, timing, lab debug, and system integration

You have a track record of taking complex hardware/software integration problems from ambiguity to root cause and closure

You write clean, maintainable RTL, scripts, documentation, and interface definitions that other engineers can build on

You are effective in the lab and can isolate whether an issue belongs to the FPGA, board, cable, instrument, software interface, or test configuration

You mentor others, raise the technical standard of the team, and help shape reusable platform capabilities

You communicate clearly across disciplines and can translate between systems needs, electrical constraints, FPGA implementation, and test objectives

You identify opportunities to use automation and AI tools to improve engineering efficiency, debug workflows, and platform maturity

Our Commitment to You:

An exciting career path with opportunities for continuous learning and development.

Research oriented work, alongside award winning teams developing practical solutions for our nation’s security

Flexible schedules with every other Friday off work, if desired (9/80 schedule)

Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more

See more at gdmissionsystems.com/careers/why-work-for-us/benefits

Workplace Options:This position is 100% Onsite or Flex as required.While on-site, you will be a part of the Scottsdale, AZ location

Salary Note
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range
USD $114,441.00 - USD $126,958.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!