Advanced ASIC FPGA Design Engineer

Scottsdale, AZ DEFENSE Full-time Posted Sep 17, 2026
Apply on General Dynamics Mission Systems (opens in a new tab) Sourced via careers-gdms.icims.com · Posted 2026-09-17

About this role

General Dynamics Mission Systems is hiring a Advanced ASIC FPGA Design Engineer, full-time, on-site in Scottsdale, AZ, in the DEFENSE sector.

Basic Qualifications

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.

CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

What You'll Do

Architect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families.

Perform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming, floorplanning, and physical optimization

Develop and execute block-level simulations using QuestaSim/ModelSim with code coverage analysis (statement, branch, condition, expression)

Create self-checking testbenches for correctness verification

Design high-speed interfaces for inter-module communication and system integration

Collaborate with systems engineers, software developers, and verification engineers in an Agile development environment

Participate in design reviews, peer code reviews, and documentation of design specifications and interface control documents

Contribute to CI/CD pipeline development for automated synthesis, simulation regression, and coverage tracking

Support integration and lab bring-up activities, including on-target FPGA debug using ILAs and JTAG-based tools

Required Qualifications

Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design

Hands-on experience with Xilinx Vivado Design Suite or Microchip Libero for synthesis, implementation, and timing analysis

Experience targeting Xilinx and Microchip device families

Ability to achieve timing closure on designs at 300+ MHz clock rates

Experience with FPGA simulation tools (QuestaSim or ModelSim)

Proficiency in writing self-checking testbenches with automated pass/fail determination

Understanding of high-speed digital design principles: pipelining, clock domain crossing (CDC), metastability mitigation, and synchronous design

Experience with AXI-Stream, AXI4, or similar on-chip bus protocols

Ability to read and interpret timing reports, utilization summaries, and critical-path analysis output

Strong written and verbal communication skills for design documentation and technical presentations

S. Citizenship and ability to obtain/maintain a Secret security clearance

Preferred Qualifications

Experience with cryptographic algorithm implementation in hardware (AES, GCM, SHA, ECC, RSA, or similar)

Experience with high-speed serial interfaces: PCIe, Ethernet (10G/25G/100G), Fibre Channel, Aurora, or GTY/GTM transceivers

Experience with CI/CD pipelines for FPGA development (GitLab CI) including automated synthesis and regression testing

Proficiency in scripting languages (Tcl, Python, Bash) for build automation and design flow scripting

Experience with version control systems (GitLab) and collaborative development workflows

Experience with Xilinx IP cores: FIFO Generator, Clock Wizard, MIG/DDR controllers, DMA/Bridge subsystems

Experience with embedded processors in FPGA (MicroBlaze, Zynq PS, Versal AI Engine)

#CJ3

Salary Note
This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range
USD $135,396.00 - USD $150,205.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Description from General Dynamics Mission Systems's official posting. Always confirm details on the company careers page.

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About General Dynamics Mission Systems

General Dynamics Mission Systems

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About Larry Sherwood Jr.

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